# project 名
PRJ ?= myprj
# board 名
BOARD ?= pynq
# standalone 模式
STANDALONE = true

# NutShell SoC Verilog 代码路径
VERILOG = NutShell/build/TopMain.v

$(VERILOG):
	make -C NutShell/ BOARD=$(BOARD) verilog

.PHONY:verilog
verilog:$(VERILOG)


# 所有 Vivado 工程路径
VIVADO_PROJECTS_PATH=NutShell/fpga/board

# Vivado 工程文件
XPR=$(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/$(PRJ)-$(BOARD).xpr

# 生成一个Vivado 工程
$(XPR):verilog
	make -C NutShell/fpga vivado PRJ=$(PRJ) BOARD=$(BOARD) STANDALONE=$(STANDALONE)

.PHONY:xpr
xpr:$(XPR)

# vivado 运行 journal 文件
VIVADO_JOURNAL = $(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/vivado.jou
$(VIVADO_JOURNAL):
	touch $@

# vivado 运行 log 文件
VIVADO_LOG = $(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/vivado.log
$(VIVADO_LOG):
	touch $@

xpr-gui:$(VIVADO_JOURNAL) $(VIVADO_LOG)
	vivado \
	-mode gui \
	-journal $(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/vivado.jou  \
	-log $(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/vivado.log \
	$(XPR)



# 硬件描述文件 
HDF = $(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/$(PRJ)-$(BOARD).sdk/system_top_wrapper.hdf

# 生成的 bitstream
BIT = $(VIVADO_PROJECTS_PATH)/$(BOARD)/build/$(PRJ)-$(BOARD)/$(PRJ)-$(BOARD).runs/impl_1/system_top_wrapper.bit




# 所有 Vivado SDK 工程路径
VIVADO_SDK_PROJECTS_PATH=NutShell/fpga/boot/build

tcl:
	vivado \
	-mode tcl \
	-nojournal \
	-nolog \
	-source fpga-shells/pynq/main.tcl




clean-v:
	rm $(VERILOG)

clean-xpr:
	rm $(XPR)


##### vivado -mode tcl -nojournal -nolog -source vivado.tcl -tclargs --board pynq